FPGA Firmware Differences

This page lists some of the major functional differences between the various FPGA functions on the Fusion and Fusion HPT products.

This table is based on ExaLINK Fusion firmware version 1.9.0.


Feature Function Mux Function Switch Function Fastmux
mux objects Unlimited * Unlimited 4
switch objects No Unlimited with switch license ** No
patch/tap objects Yes (<5ns) Yes (<5ns) Yes (<5ns)
mirror objects Yes Yes No
10G port support Yes Yes Yes
1G port support Yes No (planned) No
VLAN support Yes Yes No
Num upstream mux ports 4 Unlimited 4
Num mirror objects with timestamping output 4 0
Minimum cut-through latency (+/- ~3ns) 92ns
(down-up, 10G-10G, no VLAN)
86ns
(mux-object, 10G-10G, no VLAN)
39.00ns (+/- 0.25ns)
102ns
(up-down layer2 mode, 10G-10G, no VLAN)
95ns
(switch object, 10G-10G, no VLAN)
Maximum cut-through latency (+/- ~3ns) 92ns
(down-up, 10G-10G, no VLAN)
120ns
(48 port mux object, 10G-10G, no VLAN)
55.50ns (+/-0.25ns)
102ns
(up-down layer2 mode, 10G-10G, no VLAN)
126ns
(48 port switch object, 10G-10G, no VLAN)
FPGA on-chip packet buffering >=1.2MByte >=1.5MByte >=64KByte
Software sending messages through dataplane(e.g. LLDP, BGP, IGMP) Yes Yes No

* There is a limitation of 4 upstream ports with mux firmware. Please refer to Mux objects for further details.

** A switch license is required to create switch objects. A switch license is included when ordering the Fusion in the Switch SKU.

This table is based on ExaLINK Fusion HPT firmware version 1.12.0.

Feature Funtion hpt Function hpt-40g
mux objects No No
switch objects No No
mirror objects 1 1
patch/tap objects Yes (<5ns) Yes (<5ns)
Max number of 1G input ports 40 0
Max number of 10G input ports 40 24
Max number of 40G input ports 0 4*
10G output ports 1-8 (User selectable) 1-8 (User selectable)
Deep buffering 32GByte DDR4 32GByte DDR4
Timestamp precision <100ps <100ps

* 40G inputs only supported on QSFP Line Cards ports.

This page was last updated on Jul-11-2019.